1. Technical Field
The present invention relates to integrated circuit device design, and more particularly to integrated circuit design techniques to mitigate on-chip noise of such device.
2. Description of Related Art
Improvements in manufacturing processes are enabling integrated circuit devices to offer more functionality as the size of individual transistors contained therein get smaller and smaller, thus allowing more transistors to be packaged within an integrated circuit device. As the trend of integrating more functions in a single high performance integrated circuit device (also called a chip) continues, the on-chip noise condition due to switching activity on the chip has become a major new challenge. In addition, as the power density increases with each technology generation (for example, 0.25 micron line widths, 0.18 micron line widths, 0.13 micron line widths, etc.), it becomes increasingly difficult to provide adequate power distribution when the power grid structure is shrinking at a similar rate to that of the power consuming gates/transistors. High frequency noise is impeding the desired increase in clock cycle time and improved reliability for these highly integrated systems on a chip. In order to optimally mitigate the noise impact, a systematic chip-wide approach is needed since the worst conditions anywhere on the chip will become the ultimate limiter or bottleneck.
Today, a highly integrated chip typically contains greater than 100,000 placeable objects or macros. In order to analyze and optimize the interaction between these objects/macros, a computer database with reduced memory usage and a highly efficient algorithm is needed.